In general, binning refers to measuring semiconductor devices for certain parameters and placing a specific device into different categories or “bins” according to the measured parameters. Most familiar of these methods are the speed grades offered on microprocessors such as Intel's Pentium processor which is offered in a number of speed-grades depending on the measured performance. Binning can also be performed for a variety of measurable parameters in addition to performance/speed-grading, such as power consumption, current leakage, or ability to operate at certain temperature extremes, to determine that a certain degree of functionality to be guaranteed when required.
Among digital semiconductor devices, standard products are often offered in a variety of speed grades (bins) at different prices—the higher performance devices selling for a premium. ASICs however, have never been offered in different speed grades, the assumption being that the performance of a completed device could fall anywhere within the overall process performance window. For Standard Cells, the type of ASIC that has grown the most in popularity over the last decade, this is certainly true. A standard cell requires all of the masks for the fabrication process to be custom for the particular customer application. Since these devices are custom for a particular customer's application, all the devices on a wafer must be purchased by that customer, hence there has never been a way to bin for Standard Cells.
However, there are other types of ASIC technology that that are semi-custom, that is they are partially prefabricated, requiring only the metal layers or a subset of the metal layers to be customized in order to adapt the ASIC devices to a particular customer application. Prior to this final customization, the devices on all such wafers are the same, regardless of the final customer application.
Semi-custom ASICs typically have all of the diffusion/poly layers and sometimes some or most of the metal layers in common for all the wafers in a boat (a boat is a group of wafers that are processed at the same time and/or under very similar conditions). As a result, most of the diffusion-related performance level, and some of the metal layer-related performance level, will essentially be common to all wafers in a boat since the diffusion layers and common metal layers were applied at the same time by the same equipment. Other parameters, such as power consumption and or current leakage, will also be similar for all wafers in a boat.
“Wafer banking” refers to storing partially completed ASIC wafers prior to application of whatever metal layers are required for final customization. Traditional Gate Arrays are banked prior to application of any metal layers, so the performance effect related to the metal layers on one wafer is not related to that of wafers that are metalized on a different day or using different equipment. However, it is known that most of the variation in performance between wafer runs is due to process variations in building the diffusion and poly layers as opposed to the metal layers. ASICs that have more metal layers applied prior to banking will show even less variation between wafers in a boat.
Little art exists for binning partially completed ASIC wafers as evidenced by U.S. Pat. Nos. 6,399,400 and 6,133,582 previously granted to this inventor. U.S. Pat. Nos. 6,399,400 and 6,133,582 refer to testing partially completed wafers before the final metal layers are applied. Unfortunately, in a typical semiconductor fab environment, this requires the wafers to be removed from the fab for testing and then re-introduced to the fab for final customization—a procedure that is impractical today. An alternate method is required for binning semi-custom ASICs, one that does not require wafers to be removed from the fab environment until all processing steps have been completed.